Standard interposer fabrication for 3-D stacking makes use of a complex process that includes both front and backside wafer level processing, through-Si vias to connect the front side to the backside, and a “handle-wafer” methodology that protects the front side during the backside wiring fabrication. In known processes, the backside silicon is removed by a physical chemical mechanical planarization process, reducing the full wafer thickness from about 750 um down to 50-100 um before the handle-wafer is applied and the backside wiring is formed while the wafer is still intact. Upon completion of backside wiring and bumping processes, the handle wafer is removed just prior to segmenting of the wafer into individual interposer units by a dicing process.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.